MULTIJUNCTION TIMERS
10.3 TOP (Output-Related 16-Bit Timer)
10
10.3.10 Operation in TOP Delayed Single-shot Output Mode (with Correction Function)
(1) Outline of TOP delayed single-shot output mode
In delayed single-shot output mode, the timer generates a pulse in width of (reload register set value + 1)
after a finite time equal to (counter set value + 1) only once and then stops.
When the timer is enabled (by writing to the enable bit in software or by external input) after setting the
counter and reload register, it starts counting down from the counter’s set value synchronously with the count
clock. The first time the counter underflows, it is loaded with the reload register value and continues counting
down. The counter stops when it underflows next time.
The F/F output waveform in delayed single-shot output mode is inverted (F/F output level changes from low to high
or vice versa) when the counter underflows first time and next, generating a single-shot pulse waveform in width
of (reload register set value + 1) after a finite time equal to (first set value of counter + 1) only once.
An interrupt request can be generated when the counter underflows first time and next.
The (counter set value + 1) and (reload register set value + 1) are effective as count values.
For example, if the initial counter value is 4 and the initial reload register value is 5, then the timer operates as
shown below.
Count value = (4 + 1) + (5 + 1) = 11
1
2
3
4
5
6
7
8
9
10
11
Count clock
Count clock
dependent delay
Enable
H'FFFF
(Note 1)
(5)
4
4
Counter
3
3
2
2
1
1
0
5
0
Reload
register
F/F output
Interrupt request
Underflow
Underflow
Note 1: What actually is seen in the cycle immediately after reload is the previous counter value, and not 7.
Note: • This diagram does not show detailed timing information.
Figure 10.3.12 Example of Counting in TOP Delayed Single-shot Output Mode
32180 Group User’s Manual (Rev.1.0)
10-86
RENESAS [ RENESAS TECHNOLOGY CORP ]
