MULTIJUNCTION TIMERS
10.3 TOP (Output-Related 16-Bit Timer)
10
In the example below, the reload register is initially set to H’FFF8. When the timer starts, the reload register
value is loaded into the counter, letting it start counting down. In the diagram below, the value H’0014 is
written to the correction register when the counter has counted down to H’FFF0. As a result of this correction,
the count overflows to H’0004 and the counter fails to count correctly. Also, an interrupt request is generated
for an erroneous overflowed count.
Enabled
Disabled
(by underflow)
(by writing to the enable bit
or by external input)
Count clock
Enable bit
Write to the
correction register
Overflow occurs
H'(FFF0+0014)
H'FFFF
H'FFFF
H'FFF8
H'(FFF8-1)
Undefined
H'FFF0
value
Counter
H'0004
Actual count after overflow
H'0000
Reload register
H'FFF8
Correction register
Undefined
H'0014
F/F output
Data inverted
by enable
Data inverted
by underflow
TOP interrupt request
due to underflow
Note: • This diagram does not show detailed timing information.
Figure 10.3.11 Example of an Operation in TOP Single-shot Output Mode Where Count Overflows Due to Correction
32180 Group User’s Manual (Rev.1.0)
10-85
RENESAS [ RENESAS TECHNOLOGY CORP ]
