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M32180F8TFP 参数 Datasheet PDF下载

M32180F8TFP图片预览
型号: M32180F8TFP
PDF下载: 下载PDF文件 查看货源
内容描述: 32位RISC单芯片微型计算机M32R系列M32R / ECU系列 [32-Bit RISC Single-Chip Microcomputers M32R Family M32R/ECU Series]
分类和应用: 计算机
文件页数/大小: 839 页 / 3694 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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DMAC  
9.2 DMAC Related Registers  
9
9.2.2 DMA Software Request Generation Registers  
DMA0 Software Request Generation Register (DM0SRI)  
DMA1 Software Request Generation Register (DM1SRI)  
DMA2 Software Request Generation Register (DM2SRI)  
DMA3 Software Request Generation Register (DM3SRI)  
DMA4 Software Request Generation Register (DM4SRI)  
DMA5 Software Request Generation Register (DM5SRI)  
DMA6 Software Request Generation Register (DM6SRI)  
DMA7 Software Request Generation Register (DM7SRI)  
DMA8 Software Request Generation Register (DM8SRI)  
DMA9 Software Request Generation Register (DM9SRI)  
<Address: H’0080 0460>  
<Address: H’0080 0462>  
<Address: H’0080 0464>  
<Address: H’0080 0466>  
<Address: H’0080 0468>  
<Address: H’0080 0470>  
<Address: H’0080 0472>  
<Address: H’0080 0474>  
<Address: H’0080 0476>  
<Address: H’0080 0478>  
b0  
?
1
?
2
?
3
?
4
?
5
?
6
?
7
8
9
?
10  
?
11  
?
12  
?
13  
?
14  
?
b15  
?
DM0SRI–DM9SRI  
?
?
<After reset: Undefined>  
b
Bit Name  
Function  
R
H
W
W
0–15  
DM0SRI–DM9SRI  
DMA software request generation bits  
Note: • This register may be accessed in either bytes or halfwords.  
DMA transfer request is generated by writing any  
data to these bits.  
The DMA Software Request Generation Register is used to generate DMA transfer requests in software. A DMA  
transfer request can be generated by writing any data to this register when “Software start” has been selected  
for the cause of DMA transfer request.  
(1) DM0SRI–DM9SRI (DMA Software Request Generation) bits  
A software DMA transfer request is generated by writing any data to this register in halfword (16 bits) or in  
byte (8 bits) beginning with an even or odd address when “Software start” is selected as the cause of DMA  
transfer request (by setting the DMAn Channel Control Register 0 bits 2–3 to ‘00’).  
32180 Group User’s Manual (Rev.1.0)  
9-18  
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