Section 17 I2C Bus Interface 2 (IIC2)
3. Read ICDRR every time RDRF is set. If 8th receive clock pulse falls while RDRF is 1, SCL is
fixed low until ICDRR is read. The change of the acknowledge before reading ICDRR, to be
returned to the master device, is reflected to the next transmit frame.
4. The last byte data is read by reading ICDRR.
SCL
(Master output)
9
1
2
3
4
5
6
7
8
9
1
SDA
(Master output)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
SCL
(Slave output)
SDA
(Slave output)
A
A
RDRF
ICDRS
ICDRR
Data 1
Data 2
Data 1
User
processing
[2] Read ICDRR
[2] Read ICDRR (dummy read)
Figure 17.11 Slave Receive Mode Operation Timing (1)
SCL
(Master output)
9
1
2
3
4
5
6
7
8
9
SDA
(Master output)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SCL
(Slave output)
SDA
(Slave output)
A
A
RDRF
ICDRS
ICDRR
Data 2
Data 1
Data 1
User
processing
[3] Set ACKBT
[4] Read ICDRR
[3] Read ICDRR
Figure 17.12 Slave Receive Mode Operation Timing (2)
Rev. 3.00 Sep. 10, 2007 Page 353 of 528
REJ09B0216-0300
RENESAS [ RENESAS TECHNOLOGY CORP ]
