Section 17 I2C Bus Interface 2 (IIC2)
Master transmit mode
Master receive mode
SCL
(Master output)
9
1
2
3
4
5
6
7
8
9
1
SDA
(Master output)
A
SDA
(Slave output)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
A
TDRE
TEND
TRS
RDRF
ICDRS
Data 1
ICDRR
User
Data 1
[3] Read ICDRR
[2] Read ICDRR (dummy read)
processing
[1] Clear TDRE after clearing
TEND and TRS
Figure 17.7 Master Receive Mode Operation Timing (1)
Rev. 3.00 Sep. 10, 2007 Page 349 of 528
REJ09B0216-0300