10.3.2 Description of Areas
Area 0: Area 0 physical address bits A28–A26 are 000. Address bits A31–A29 are ignored and
the address range is H'00000000 + H'20000000 × n – H'03FFFFFF + H'20000000 × n (n = 0–6
and n = 1–6 are the shadow spaces).
Ordinary memories such as SRAM, ROM, and burst ROM can be connected to this space. Byte,
word, or longword can be selected as the bus width using external pins MD3 and MD4. When the
area 0 space is accessed, the CS0 signal is asserted. The RD signal that can be used as OE and the
WE0–WE3 signals for write control are also asserted. The number of bus cycles is selected
between 0 and 10 wait cycles using the A0W2–A0W0 bits in WCR2. When the burst function is
used, the bus cycle pitch of the burst cycle is determined within a range of 2–10 according to the
number of waits.
Area 1: Area 1 physical address bits A28–A26 are 001. Address bits A31–A29 are ignored and
the address range is H'04000000 + H'20000000 × n – H'07FFFFFF + H'20000000 × n (n = 0–6
and n = 1–6 are the shadow spaces).
Area 1 is the area specifically for internal peripheral modules. External memories cannot be
connected.
Control registers of the peripheral modules shown below are mapped to this area 1. Their
addresses are physical addresses, to which logical addresses can be mapped when the MMU is
enabled:
DMAC, PORT, IrDA, SCIF, ADC, DAC, INTC (except INTEVT, IPRA, IPRB)
These registers must be set not to be cached by using software.
Area 2: Area 2 physical address bits A28–A26 are 010. Address bits A31–A29 are ignored and
the address range is H'08000000 + H'20000000 × n – H'0BFFFFFF + H'20000000 × n (n = 0–6
and n = 1–6 are the shadow spaces).
Ordinary memories such as SRAM and ROM, as well as synchronous DRAM, can be connected
to this space. Byte, word, or longword can be selected as the bus width using bits A2SZ1 and
A2SZ0 in BCR2 for ordinary memory.
When the area 2 space is accessed, the CS2 signal is asserted. When ordinary memories are
connected, the RD signal that can be used as OE and the WE0–WE3 signals for write control are
also asserted and the number of bus cycles is selected between 0 and 3 wait cycles using bits
A2W1 and A2W0 bits in WCR2. Only when ordinary memories are connected, any way can be
inserted in each bus cycle by means of the external wait pin (WAIT).
When synchronous DRAM is connected, the RAS3U and RAS3L signals, CASU and CASL
signals, RD/WR signal, and byte control signals DQMHH, DQMHL, DQMLH, and DQMLL are
all asserted and addresses multiplexed. Control of RAS3U, RAS3L, CASU, CASL, data timing,
and address multiplexing is set with MCR.
Rev. 5.00, 09/03, page 265 of 760
RENESAS [ RENESAS TECHNOLOGY CORP ]
