Table 10.9 8-Bit External Device/Big-Endian Access and Data Alignment
Data Bus
Strobe Signals
D31– D23– D15–
WE3,
DQMUU
WE2,
DQMUL
WE1,
DQMLU
WE0,
Operation
D24
D16
D8
—
—
—
—
—
D7–D0
DQMLL
Byte access at 0
Byte access at 1
Byte access at 2
Byte access at 3
Word access 1st time
—
—
Data 7–0
Data 7–0
Data 7–0
Data 7–0
Asserted
Asserted
Asserted
Asserted
Asserted
—
—
—
—
—
—
—
—
Data
15–8
at 0
at 0
2nd time —
at 1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Data
7–0
Asserted
Asserted
Asserted
Asserted
Asserted
Asserted
Asserted
Word access 1st time
—
Data
15–8
at 2
at 2
2nd time —
at 3
Data
7–0
Longword
access at 0
1st time
at 0
—
Data
31–24
2nd time —
at 1
Data
23–16
3rd time
at 2
—
Data
15–8
4th time
at 3
—
Data
7–0
Rev. 5.00, 09/03, page 262 of 760