Table 10.12 8-Bit External Device/Little-Endian Access and Data Alignment
Data Bus
Strobe Signals
D31–
D24
D23–
D15–D8
WE3,
D7–D0 DQMUU
WE2,
DQMUL
WE1,
DQMLU
WE0,
DQMLL
Operation
D16
Byte access at 0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Data
7–0
Asserted
Asserted
Asserted
Asserted
Asserted
Asserted
Asserted
Asserted
Asserted
Asserted
Asserted
Asserted
Byte access at 1
—
—
—
—
—
—
—
—
—
—
—
—
Data
7–0
Byte access at 2
—
Data
7–0
Byte access at 3
—
Data
7–0
Word access 1st time
—
Data
7–0
at 0
at 0
2nd time
at 1
—
Data
15–8
Word access 1st time
—
Data
7–0
at 2
at 2
2nd time
at 3
—
Data
15–8
Longword
1st time
at 0
—
Data
7–0
access at 0
2nd time
at 1
—
Data
15–8
3rd time
at 2
—
Data
23–16
4th time
at 3
—
Data
31–24
Rev. 5.00, 09/03, page 264 of 760