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HD6417709SF133B 参数 Datasheet PDF下载

HD6417709SF133B图片预览
型号: HD6417709SF133B
PDF下载: 下载PDF文件 查看货源
内容描述: 瑞萨32位RISC单片机超级RISC引擎族/ SH7700系列 [Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 807 页 / 4409 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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Bit 6—Timer Mode Select (WT/IT): Selects whether to use the WDT as a watchdog timer or an  
interval timer.  
Bit 6: WT/IT  
Description  
0
Used as interval timer  
Used as watchdog timer  
(Initial value)  
1
Note: If WT/IT is modified when the WDT is running, the up-count may not be performed correctly.  
Bit 5—Reset Select (RSTS): Selects the type of reset when WTCNT overflows in watchdog  
timer mode. In interval timer mode, this setting is ignored.  
Bit 5: RSTS  
Description  
Power-on reset  
Manual reset  
0
1
(Initial value)  
Note: RESETOUT is output.  
Bit 4—Watchdog Timer Overflow (WOVF): Indicates that the WTCNT has overflowed in  
watchdog timer mode. This bit is not set in interval timer mode.  
Bit 4: WOVF  
Description  
0
1
No overflow  
(Initial value)  
WTCNT has overflowed in watchdog timer mode  
Bit 3—Interval Timer Overflow (IOVF): Indicates that WTCNT has overflowed in interval  
timer mode. This bit is not set in watchdog timer mode.  
Bit 3: IOVF  
Description  
0
1
No overflow  
(Initial value)  
WTCNT has overflowed in interval timer mode  
Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select the clock to be used for the  
WTCNT count from the eight types obtainable by dividing the peripheral clock. The overflow  
period in the table is the value when the peripheral clock (Pφ) is 15 MHz.  
Rev. 5.00, 09/03, page 216 of 760  
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