Cautions:
1. The frequency of the internal clock (Iφ) becomes:
•
The product of the frequency of the CKIO pin, the frequency multiplication ratio of PLL
circuit 1, and the division ratio of divider 1.
•
Do not set the internal clock frequency lower than the CKIO pin frequency.
2. The frequency of the peripheral clock (Pφ) becomes:
•
The product of the frequency of the CKIO pin, the frequency multiplication ratio of PLL
circuit 1, and the division ratio of divider 2.
•
The peripheral clock frequency should not be set higher than the frequency of the CKIO
pin, higher than 33.34 MHz.
3. The output frequency of PLL circuit 1 is the product of the CKIO frequency and the
multiplication ratio of PLL circuit 1.
4. × 1, × 2, × 3, × 4, or × 6 can be used as the multiplication ratio of PLL circuit 1. × 1, × 1/2,
× 1/3, × 1/4, and × 1/6 can be selected as the division ratios of dividers 1 and 2. Set the rate in
the frequency control register. The on/off state of PLL circuit 2 is determined by the mode.
Rev. 5.00, 09/03, page 210 of 760
RENESAS [ RENESAS TECHNOLOGY CORP ]
