9.2.2
CPG Pin Configuration
Table 9.1 lists the CPG pins and their functions.
Table 9.1 CPG Pins and Functions
Pin Name
Symbol
MD0
I/O
Description
Mode control
pins
I
Set the clock operating mode
MD1
I
MD2
I
Crystal I/O pins
(clock input pins)
XTAL
EXTAL
O
I
Connects a crystal oscillator
Connects a crystal oscillator. Also used to input an
external clock
Clock I/O pin
CKIO
CAP1
I/O
I
Inputs or outputs an external clock
Capacitor
connection pins
for PLL
Connects capacitor for PLL circuit 1 operation
(recommended value 470 pF)
CAP2
I
Connects capacitor for PLL circuit 2 operation
(recommended value 470 pF)
9.2.3
CPG Register Configuration
Table 9.2 shows the CPG register configuration.
Table 9.2 CPG Register
Register Name
Abbreviation R/W Initial Value Address
Access Size
Frequency control register
FRQCR R/W H'0102 H'FFFFFF80 16
Rev. 5.00, 09/03, page 206 of 760
RENESAS [ RENESAS TECHNOLOGY CORP ]
