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HD6417709SF133B 参数 Datasheet PDF下载

HD6417709SF133B图片预览
型号: HD6417709SF133B
PDF下载: 下载PDF文件 查看货源
内容描述: 瑞萨32位RISC单片机超级RISC引擎族/ SH7700系列 [Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 807 页 / 4409 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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Section  
Page  
Description  
16.4 SCIF Interrupts  
550  
Description amended  
When the TDFE flag in the serial status register (SCSSR) is set to  
1, a TXI interrupt request is generated. The DMAC can be  
activated and data transfer performed when this interrupt is  
generated. When data exceeding the transmit trigger number is  
written to the transmit data register (SCFTDR) by the DMAC, 1 is  
read from the TDFE flag, after which 0 is written to it to clear it.  
When the RDF flag in SCSSR is set to 1, an RXI interrupt request  
is generated. The DMAC can be activated and data transfer  
performed when the RDF flag in SCSSR is set to 1. When  
receive data less than the receive trigger number is read from the  
receive data register (SCFRDR) by the DMAC, 1 is read from the  
RDF flag, after which 0 is written to it to clear it.  
16.5 Usage Notes  
551  
Description amended  
1. SCFTDR Writing and TDFE Flag:  
However, if the number of data bytes written to SCFTDR is equal  
to or less than the transmit trigger number, the TDFE flag will be  
set to 1 again even after having been cleared to 0. TDFE clearing  
should therefore be carried out after data exceeding the specified  
transmit trigger number has been written to SCFTDR.  
2. SCFRDR Reading and RDF Flag:  
However, if the number of data bytes in SCFRDR exceeds the  
trigger number, the RDF flag will be set to 1 again even after  
having been cleared to 0. RDF should therefore be cleared to 0  
after being read as 1 after all the receive data has been read.  
19.13.2 SC Port Data 610  
Register (SCPDR)  
Title Amended  
Rev. 5.0, 09/03, page xiii of xliv  
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