Section
Page
115,
116
Description
5.4.3 Examples of
Usage
(1) Invalidating a Specific Entry
Description amended
A specific cache entry can be invalidated by accessing the allocated
memory cache and writing a 0 to the entry’s U and V bits. The A bit is
cleared to 0, and an address is specified for the entry address and the
way. If the U bit of the way of the entry in question was set to 1, the
entry is written back and the V and U bits specified by the write data are
written to.
In the following example, the write data is specified in R0 and the
address is specified in R1.
; R0 = H'0000 0000 LRU = H'000, U = 0, V = 0
; R1 = H'F000 1080, Way = 1, Entry = H'08, A = 0
;
MOV.L R0, @R1
To invalidate all entries and ways, write 0 to the following addresses.
Addresses
F000 0000
F000 0010
F000 0020
:
F000 3FF0
This involves a total of 1,024 writes.
The above operation should be performed using a non-cacheable area.
(2) Invalidating a Specific Address
Newly added
(3) Reading Data from a Specific Entry
Description amended
; R0 = H'F100 004C; Data array access, Entry = H'04,
; Way = 0, Longword address = 3
;
MOV.L R0, @R1
; Longword 3 is read.
6.2.6 Interrupt
127
Exception Handling and
Priority
Table 6.4 Interrupt
Exception Handling
Sources and Priority
(IRQ Mode)
6.3.6 Interrupt
Request Register 0
(IRR0)
138
IPR (bit numbers) for SCI amended
(Before)IPRB(3-0)
→
(After)IPRB(7-4)
Description amended
When clearing an IRQ5R–IRQ0R bit to 0, read the bit while bit set
to 1, and then write 0. In this case, 0 should be written only to the
bits to be cleared and 1 to the other bits. The contents of the bits
to which 1 is written do not change.
Description added
Bit 1—Module Standby 1 (MSTP1)
Before switching the RTC to module standby, access at least one
among the registers RTC, SCI, and TMU.
8.2.1 Standby Control
184
Register (STBCR)
Rev. 5.0, 09/03, page x of xliv
RENESAS [ RENESAS TECHNOLOGY CORP ]
