Trc
Trc
TRs1
TRs2
TRs3
TRs4
TRs5
Trc
CKIO
tAD
tAD
BANK
Precharge-sel
Address
tCSD
tCSD
tCSD
tCSD
tRWD
tRWD
RD/
tRASD
tRASD
tRASD
tRASD
tCASD2
tCASD2
tCASD2
tCASD2
tDQMD
tDQMD
DQMn
tWDD
tWDD
D63–D0
(write)
tBSD
tCKED
tCKED
CKE
tDACD
tDACD
DACKn
Notes: IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high
Figure 22.35 Synchronous DRAM Bus Cycle: Synchronous DRAM Self-Refresh
(TRC[2:0] = 001)
Rev. 6.0, 07/02, page 897 of 986