Trwl
Trwl
Tpr
Tpc
Tr
Trw
Tc1
Tc2
Tc3
Tc4
CKIO
tAD
tAD
tAD
BANK
Row
Row
tAD
Precharge-sel
H/L
Row
Row
H/L
Address
c0
tCSD
tCSD
tRWD
tRWD
tRWD
tRWD
RD/
tRASD tRASD tRASD tRASD
tCASD2 tCASD2
tCASD2
tDQMD
tDQMD
DQMn
tWDD
tWDD
tWDD
D63–D0
(write)
d0
d1
d2
d3
tBSD
tBSD
CKE
tDACD
tDACD
tDACD
DACKn
(SA: IO → memory)
Notes: IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high
Figure 22.31 Synchronous DRAM Normal Write Bus Cycle: PRE + ACT + WRITE
Commands, Burst (RCD[1:0] = 01, TPC[2:0] = 001, TRWL[2:0] = 010)
Rev. 6.0, 07/02, page 893 of 986