TMw4
TMw5
TRp1
TRp2
TRp3
TRp4
TMw
TMw2
TMw3
CKIO
tAD
tAD
tAD
BANK
Precharge-sel
Address
tCSD
tCSD
tCSD
tRWD
tRWD
tRWD
RD/
tRASD
tRASD
tRASD
tCASD2
tCASD2
tCASD2
tCASD2
tDQMD
tDQMD
DQMn
tWDD
tWDD
D63–D0
(write)
tBSD
CKE
tDACD
tDACD
DACKn
Notes: IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high
Figure 22.36 (a) Synchronous DRAM Bus Cycle: Synchronous DRAM Mode Register
Setting (PALL)
Rev. 6.0, 07/02, page 898 of 986