Trwl
Trwl
Tnop
(Tnop)
Tc1
Tc2
Tc3
Tc4
CKIO
tAD
tAD
BANK
Row
Precharge-sel
H/L
c0
Address
tCSD
tCSD
tRWD
tRWD
RD/
tCASD2
tCASD2
tDQMD
tDQMD
DQMn
tWDD
tWDD
tWDD
D63–D0
(write)
d0
d1
d2
d3
tBSD
tBSD
CKE
SA-DMA
tDACD
tDACD
DACKn
(SA: IO → memory)
Normal write
Notes: In the case of SA-DMA only, the (Tnop) cycle is inserted, and the DACKn signal is output as shown by the
solid line. In a normal write, the (Tnop) cycle is omitted and the DACKn signal is output as shown by the
dotted line.
IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high
Figure 22.32 Synchronous DRAM Normal Write Bus Cycle: WRITE Command, Burst
(TRWL[2:0] = 010)
Rev. 6.0, 07/02, page 894 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
