Trc
Trc
TRr1
TRr2
TRr3
TRr4
TRrw
TRr5
Trc
CKIO
tAD
tAD
BANK
Precharge-sel
Address
tCSD
tCSD
tCSD
tCSD
tRWD
tRWD
RD/
tRASD
tRASD
tRASD
tRASD
tCASD2 tCASD2 tCASD2
tCASD2
tDQMD
tDQMD
DQMn
tWDD
tWDD
D63–D0
(write)
tBSD
CKE
tDACD
tDACD
DACKn
Notes: IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high
Figure 22.34 Synchronous DRAM Bus Cycle: Synchronous DRAM Auto-Refresh
(TRAS = 1, TRC[2:0] = 001)
Rev. 6.0, 07/02, page 896 of 986