Tce
Tpc
T1r
Tr2
Tc1
Tc2
CKIO
tAD
tAD
tAD
Row
Column
A25–A0
tCSD
tCSD
tRWD
tRWD
RD/
tRASD tRASD
tRASD
tCASD1
tCASD1
tCASD1
tRDS
tRDH
D63–D0
(read)
tWDD
D63–D0
(write)
tBSD
tBSD
tDACD
tDACD
DACKn
(SA: IO ← memory)
Notes: IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high
Figure 22.38 DRAM Bus Cycle
(EDO Mode, RCD[1:0] = 00, AnW[2:0] = 000, TPC[2:0] = 001)
Rev. 6.0, 07/02, page 901 of 986