Reset or NMI
interrupt request
Stable input clock
Stable input clock
EXTAL input
t
PLL × 2
PLL synchronization
PLL synchronization
PLL output,
CKIO output
Internal clock
STATUS1–
STATUS0
Normal
Standby
Normal
Note: When external clock from EXTAL is input
Figure 22.9 PLL Synchronization Settling Time in Case of 5(6(7 or NMI Interrupt
–
interrupt request
Stable input clock
Stable input clock
EXTAL input
PLL synchronization
tIRLSTB
PLL synchronization
t
PLL × 2
PLL output,
CKIO output
Internal clock
STATUS1–
STATUS0
Normal
Standby
Normal
Note: When external clock from EXTAL is input
Figure 22.10 PLL Synchronization Settling Time in Case of IRL Interrupt
Rev. 6.0, 07/02, page 866 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
