Table 22.34 Control Signal Timing (2)
HD6417750
F167
HD6417750
F167I
HD6417750
SF167
HD6417750
SVF133
HD6417750
SF167I
HD6417750
BP200M
HD6417750
VF128
HD6417750
SVBT133
HD6417750
SF200
HD6417750
SBP200
1
1
2
3
*
*
*
*
Item
Symbol Min Max
Min Max
Min Max
Min Max Unit Figure Notes
%5(4 setup tBREQS
3.5
1.5
—
—
—
10
15
2
3.5
1.5
—
—
—
10
15
2
3.5
1.5
—
—
—
8
3
—
—
6
ns
ns
ns
ns
tcyc
22.13
22.13
22.13
22.13
22.14
time
%5(4 hold
tBREQH
1.5
—
—
—
time
%$&. delay tBACKD
time
Bus tri-state
delay time
tBOFF1
tBOFF2
—
—
—
12
2
10
2
Bus tri-state
delay time
to standby
mode
—
—
—
Bus buffer
on time
tBON1
tBON2
—
—
15
1
—
—
15
1
—
—
12
1
—
—
10
1
ns
tcyc
22.13
22.14
Bus buffer
on time from
standby
STATUS0/1
delay time
tSTD1
tSTD2
—
—
11
2
—
—
11
2
—
—
9
2
—
—
7
2
ns
tcyc
22.14
22.14
STATUS0/1
delay time
to standby
Notes: *1 VDDQ = 3.0 to 3.6 V, VDD = typ. 1.5 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on
*2 VDDQ = 3.0 to 3.6 V, VDD = typ. 1.8 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on
(HD6417750F167, HD6417750SF167, HD6417750SF200)
VDDQ = 3.0 to 3.6 V, VDD = typ. 1.8 V, Ta = –40 to +85°C, CL = 30 pF, PLL2 on
(HD6417750F167I, HD6417750SF167I)
*3 VDDQ = 3.0 to 3.6 V, VDD = typ. 1.8 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on
Rev. 6.0, 07/02, page 869 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
