Stable oscillation
CKIO,
internal clock
VDD min
VDD
tRESW
tOSC1
tSCK2RH
SCK2
tOSCMD
tMDRH
MD8, MD7,
MD2–MD0
tTRSTRH
Notes: 1. Oscillation settling time when on-chip resonator is used
2. PLL2 not operating
Figure 22.3 Power-On Oscillation Settling Time
Standby
Stable oscillation
CKIO,
internal clock
tRESW
tOSC2
Notes: 1. Oscillation settling time when on-chip resonator is used
2. PLL2 not operating
Figure 22.4 Standby Return Oscillation Settling Time (Return by 5(6(7)
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