Stable oscillation
Internal clock
VDD
VDD min
tRESW
tOSC1
tSCK2RH
SCK2
tOSCMD
tMDRH
MD8, MD7,
MD2–MD0
tTRSTRH
CKIO
Notes: 1. Oscillation settling time when on-chip resonator is used
2. PLL2 operating
Figure 22.5 Power-On Oscillation Settling Time
Stable oscillation
Standby
Internal
clock
tRESW
tOSC2
CKIO
Notes: 1. Oscillation settling time when on-chip resonator is used
2. PLL2 operating
Figure 22.6 Standby Return Oscillation Settling Time (Return by 5(6(7)
Rev. 6.0, 07/02, page 864 of 986