SH7750R:
Bit:
15
TI7
1
14
TI6
1
13
TI5
1
12
TI4
1
11
TI3
1
10
TI2
1
9
TI1
1
8
TI0
1
Initial value:
R/W:
R
R
R
R
R
R
R
R
Bit:
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
—
1
1
—
1
0
—
1
Initial value:
R/W:
R
R
R
R
R
R
R
R
Bits 15 to 8—Test Instruction Bits (TI7–TI0)
Bit 15: Bit 14: Bit 13: Bit 12: Bit 11: Bit 10: Bit 9: Bit 8: Description
TI7
TI6
TI5
TI4
TI3
TI2
TI1
TI0
0
0
0
0
0
0
0
0
EXTEST
0
0
0
0
0
1
0
0
SAMPLE/PRELOAD
H-UDI reset negate
H-UDI reset assert
H-UDI interrupt
0
1
1
0
—
—
—
1
—
—
—
1
—
—
—
1
—
—
—
1
0
1
1
1
1
0
1
—
1
1
1
1
Bypass mode (Initial value)
Reserved
Other than above
Bits 7 to 0—Reserved: These bits are always read as 1, and should only be written with 1.
Rev. 6.0, 07/02, page 804 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
