the rating of the pull-up resistor on port-pin f. Although this current has no effect on the
chip’s operation, unnecessary current will be dissipated.
The maximum frequency of TCK (TMS, TDI, TDO) is 20 MHz. Make the TCK or SH7750 Series
CPG setting so that the TCK frequency is lower than that of the SH7750 Series’ on-chip
peripheral module clock.
21.1.4 Register Configuration
Table 21.2 shows the H-UDI registers. Except for SDBPR, these registers are mapped in the
control register space and can be referenced by the CPU.
Table 21.2 H-UDI Registers
CPU Side
H-UDI Side
Abbre-
viation R/W Address
P4
Area 7
Address
Access Initial
Access Initial
1
1
*
*
Value
Name
Size
Value
R/W Size
Instruction
register
SDIR
R
H'FFF00000 H'1FF00000 16
H'FFFF R/W 32
H'FFFFFFFD
(Fixed
2
*
value
)
Data register SDDR/ R/W H'FFF00008 H'1FF00008 32/16
SDDRH
Unde-
fined
—
—
—
—
1
—
H
Data register SDDRL R/W H'FFF0000A H'1FF0000A 16
L
Unde-
fined
—
—
Bypass
register
SDBPR
—
—
—
—
Unde-
fined
R/W
3
*
Interrupt
source
SDINT R/W H'FFF00014 H'1FF00014 16
H'0000
W
32
H'00000000
Undefined
4
*
register
Boundary
scan register
SDBSR
—
—
—
—
Unde-
fined
R/W
—
4
*
Notes: *1 Initialized when the 7567 pin goes low or when the TAP is in the Test-Logic-Reset
state.
*2 The value read from H-UDI is fixed (H'FFFFFFFD).
*3 Using the H-UDI interrupt command, a 1 can be written to the least significant bit.
*4 SH7750R only
Rev. 6.0, 07/02, page 802 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
