Table 19.4 SH7750 ,5/6–,5/3 Pins and Interrupt Levels (When IRLM = 1)
,5/6
1/0
1/0
1/0
0
,5/5
1/0
1/0
0
,5/4
1/0
0
,5/3
Interrupt Priority Level
Interrupt Request
0
1
1
1
13
10
7
IRL0
IRL1
IRL2
IRL3
1
1
1
4
19.2.3 On-Chip Peripheral Module Interrupts
On-chip peripheral module interrupts are generated by the following nine modules:
•
•
•
•
•
•
•
•
•
Hitachi user debug interface (H-UDI)
Direct memory access controller (DMAC)
Timer unit (TMU)
Realtime clock (RTC)
Serial communication interface (SCI)
Serial communication interface with FIFO (SCIF)
Bus state controller (BSC)
Watchdog timer (WDT)
I/O port (GPIO)
Not every interrupt source is assigned a different interrupt vector, bus sources are reflected in the
interrupt event register (INTEVT), so it is easy to identify sources by using the INTEVT register
value as a branch offset in the exception handling routine.
A priority level from 15 to 0 can be set for each module by means of interrupt priority registers A
to D (IPRA–IPRD), 00 (INTPRI00).
The interrupt mask bits (I3–I0) in the status register (SR) are not affected by on-chip peripheral
module interrupt handling.
On-chip peripheral module interrupt source flag and interrupt enable flag updating should only be
carried out when the BL bit in the status register (SR) is set to 1. To prevent acceptance of an
erroneous interrupt from an interrupt source that should have been updated, first read the on-chip
peripheral register containing the relevant flag, then clear the BL bit to 0. In the case of interrupts
on channel 3 or 4 of the TMU, also read from the interrupt source register 00 (INTREQ00). This
will secure the necessary timing internally. When updating a number of flags, there is no problem
if only the register containing the last flag updated is read.
Rev. 6.0, 07/02, page 757 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
