Table 19.5 Interrupt Exception Handling Sources and Priority Order (cont)
INTEVT Interrupt Priority IPR (Bit Priority within
Default
Interrupt Source
Code
(Initial Value)
Numbers)
IPR Setting Unit Priority
2
*
*
TMU3
TMU4
TUNI3
TUNI4
H'B00
15–0 (0)
INTPRI00
(11–8)
—
—
High
↑
2
H'B80
15–0 (0)
INTPRI00
(15–12)
TMU0
TMU1
TMU2
TUNI0
TUNI1
TUNI2
H'400
H'420
H'440
H'460
H'480
H'4A0
H'4C0
H'4E0
H'500
H'520
H'540
H'700
H'720
H'740
H'760
H'560
H'580
H'5A0
15–0 (0)
15–0 (0)
15–0 (0)
IPRA (15–12)
IPRA (11–8)
IPRA (7–4)
—
—
High
Low
High
↑
↓
TICPI2
ATI
RTC
SCI1
15–0 (0)
15–0 (0)
IPRA (3–0)
IPRB (7–4)
PRI
CUI
ERI
RXI
TXI
Low
High
↑
↓
TEI
Low
SCIF
ERI
RXI
BRI
TXI
15–0 (0)
IPRC (7–4)
High
↑
↓
Low
WDT
REF
ITI
15–0 (0)
15–0 (0)
IPRB (15–12)
IPRB (11–8)
—
↓
RCMI
ROVI
High
Low
Low
Notes: TUNI0–TUNI4: Underflow interrupts
TICPI2: Input capture interrupt
ATI:
PRI:
CUI:
ERI:
RXI:
TXI:
TEI:
BRI:
ITI:
Alarm interrupt
Periodic interrupt
Carry-up interrupt
Receive-error interrupt
Receive-data-full interrupt
Transmit-data-empty interrupt
Transmit-end interrupt
Break interrupt request
Interval timer interrupt
RCMI: Compare-match interrupt
ROVI: Refresh counter overflow interrupt
Rev. 6.0, 07/02, page 760 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
