19.2
Interrupt Sources
There are three types of interrupt sources: NMI, RL, and on-chip peripheral modules. Each
interrupt has a priority level (16–0), with level 16 as the highest and level 1 as the lowest. When
level 0 is set, the interrupt is masked and interrupt requests are ignored.
19.2.1 NMI Interrupt
The NMI interrupt has the highest priority level of 16. It is always accepted unless the BL bit in
the status register in the CPU is set to 1. In sleep or standby mode, the interrupt is accepted even if
the BL bit is set to 1.
A setting can also be made to have the NMI interrupt accepted even if the BL bit is set to 1.
Input from the NMI pin is edge-detected. The NMI edge select bit (NMIE) in the interrupt control
register (ICR) is used to select either rising or falling edge. When the NMIE bit in the ICR register
is modified, the NMI interrupt is not detected for a maximum of 6 bus clock cycles after the
modification.
NMI interrupt exception handling does not affect the interrupt mask level bits (I3–I0) in the status
register (SR).
Rev. 6.0, 07/02, page 754 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
