Interrupt Operation: There are three interrupt sources in smart card interface mode, generating
transmit-data-empty interrupt (TXI) requests, transmit/receive-error interrupt (ERI) requests, and
receive-data-full interrupt (RXI) requests. The transmit-end interrupt (TEI) request cannot be used
in this mode.
When the TEND flag in SCSSR1 is set to 1, a TXI interrupt request is generated.
When the RDRF flag in SCSSR1 is set to 1, an RXI interrupt request is generated.
When any of flags ORER, PER, and FER/ERS in SCSSR1 is set to 1, an ERI interrupt request is
generated. The relationship between the operating states and interrupt sources is shown in table
17.9.
Table 17.9 Smart Card Mode Operating States and Interrupt Sources
Operating State
Flag
Mask Bit
TIE
Interrupt Source
Transmit mode
Normal operation
Error
TEND
TXI
ERI
RXI
ERI
FER/ERS
RDRF
RIE
Receive mode
Normal operation
Error
RIE
PER, ORER
RIE
Data Transfer Operation by DMAC: In smart card mode, as with the normal SCI, transfer can
be carried out using the DMAC. In a transmit operation, when the TEND flag in SCSSR1 is set to
1, a TXI interrupt is requested. If the TXI request is designated beforehand as a DMAC activation
source, the DMAC will be activated by the TXI request, and transfer of the transmit data will be
carried out. The TEND flag is automatically cleared to 0 when data transfer is performed by the
DMAC. In the event of an error, the SCI retransmits the same data automatically. The TEND flag
remains cleared to 0 during this time, and the DMAC is not activated. Thus, the number of bytes
specified by the SCI and DMAC are transmitted automatically, including retransmission following
an error. However, the ERS flag is not cleared automatically when an error occurs, and therefore
the RIE bit should be set to 1 beforehand so that an ERI request will be generated in the event of
an error, and the ERS flag will be cleared.
In a receive operation, an RXI interrupt request is generated when the RDRF flag in SCSSR1 is
set to 1. If the RXI request is designated beforehand as a DMAC activation source, the DMAC
will be activated by the RXI request, and transfer of the receive data will be carried out. The
RDRF flag is cleared to 0 automatically when data transfer is performed by the DMAC. If an error
occurs, an error flag is set but the RDRF flag is not. The DMAC is not activated, but instead, an
ERI interrupt request is sent to the CPU. The error flag must therefore be cleared.
When performing data transfer using the DMAC, it is essential to set and enable the DMAC
before carrying out SCI settings. For details of the DMAC setting procedures, see section 14,
Direct Memory Access Controller (DMAC).
Rev. 6.0, 07/02, page 724 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
