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HD6417750SBP200 参数 Datasheet PDF下载

HD6417750SBP200图片预览
型号: HD6417750SBP200
PDF下载: 下载PDF文件 查看货源
内容描述: 的SuperH RISC引擎 [SuperH RISC engine]
分类和应用: 外围集成电路时钟
文件页数/大小: 1039 页 / 6201 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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From the above equation, if F = 0 and D = 0.5, the receive margin is 49.866%, as given by the  
following equation.  
When D = 0.5 and F = 0:  
M = (0.5 – 1/2 × 372) × 100% = 49.866%  
(2) Retransfer Operations  
Retransfer operations are performed by the SCI in receive mode and transmit mode as described  
below.  
Retransfer Operation when SCI is in Receive Mode: Figure 17.11 illustrates the retransfer  
operation when the SCI is in receive mode.  
1. If an error is found when the received parity bit is checked, the PER bit in SCSSR1 is  
automatically set to 1. If the RIE bit in SCSCR1 is enabled at this time, an ERI interrupt  
request is generated. The PER bit in SCSSR1 should be cleared to 0 before the next parity bit  
is sampled.  
2. The RDRF bit in SCSSR1 is not set for a frame in which an error has occurred.  
3. If an error is found when the received parity bit is checked, the PER bit in SCSSR1 is not set to  
1.  
4. If no error is found when the received parity bit is checked, the receive operation is judged to  
have been completed normally, and the RDRF bit in SCSSR1 is automatically set to 1. If the  
RIE bit in SCSCR1 is enabled at this time, an RXI interrupt request is generated.  
5. When a normal frame is received, the pin retains the high-impedance state at the timing for  
error signal transmission.  
nth transfer frame  
Retransferred frame  
Transfer frame n+1  
(DE)  
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE  
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp  
Ds D0 D1 D2 D3 D4  
5
RDRF  
PER  
4
3
2
1
Figure 17.11 Retransfer Operation in SCI Receive Mode  
Rev. 6.0, 07/02, page 726 of 986  
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