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HD6417750SBP200 参数 Datasheet PDF下载

HD6417750SBP200图片预览
型号: HD6417750SBP200
PDF下载: 下载PDF文件 查看货源
内容描述: 的SuperH RISC引擎 [SuperH RISC engine]
分类和应用: 外围集成电路时钟
文件页数/大小: 1039 页 / 6201 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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Serial Data Reception: Data reception in smart card mode uses the same processing procedure as  
for the normal SCI. Figure 17.9 shows a sample reception processing flowchart.  
1. Perform smart card interface mode initialization as described in Initialization above.  
2. Check that the ORER flag and PER flag in SCSSR1 are cleared to 0. If either is set, perform  
the appropriate receive error handling, then clear both the ORER and the PER flag to 0.  
3. Repeat steps 2 and 3 until it can be confirmed that the RDRF flag is set to 1.  
4. Read the receive data from SCRDR1.  
5. To continue receiving data, clear the RDRF flag to 0 and go back to step 2.  
6. To end reception, clear the RE bit to 0.  
With the above processing, interrupt handling is possible.  
If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests  
are enabled, a receive-data-full interrupt (RXI) request will be generated. If an error occurs in  
reception and either the ORER flag or the PER flag is set to 1, a transmit/receive-error interrupt  
(ERI) request will be generated.  
See Interrupt Operation in section 17.3.6 below for details.  
If a parity error occurs during reception and the PER flag is set to 1, the received data is still  
transferred to SCRDR1, and therefore this data can be read.  
Rev. 6.0, 07/02, page 722 of 986  
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