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HD6417750SBP200 参数 Datasheet PDF下载

HD6417750SBP200图片预览
型号: HD6417750SBP200
PDF下载: 下载PDF文件 查看货源
内容描述: 的SuperH RISC引擎 [SuperH RISC engine]
分类和应用: 外围集成电路时钟
文件页数/大小: 1039 页 / 6201 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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Retransfer Operation when SCI is in Transmit Mode: Figure 17.12 illustrates the retransfer  
operation when the SCI is in transmit mode.  
1. If an error signal is sent back from the receiving side after transmission of one frame is  
completed, the FER/ERS bit in SCSSR1 is set to 1. If the RIE bit in SCSCR1 is enabled at this  
time, an ERI interrupt request is generated. The FER/ERS bit in SCSSR1 should be cleared to  
0 before the next parity bit is sampled.  
2. The TEND bit in SCSSR1 is not set for a frame for which an error signal indicating an error is  
received.  
3. If an error signal is not sent back from the receiving side, the FER/ERS bit in SCSSR1 is not  
set.  
4. If an error signal is not sent back from the receiving side, transmission of one frame, including  
a retransfer, is judged to have been completed, and the TEND bit in SCSSR1 is set to 1. If the  
TIE bit in SCSCR1 is enabled at this time, a TXI interrupt request is generated.  
nth transfer frame  
Retransferred frame  
Transfer frame n+1  
(DE)  
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE  
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp  
Ds D0 D1 D2 D3 D4  
TDRE  
Transfer from SCTDR1  
to SCTSR1  
Transfer from SCTDR1  
to SCTSR1  
Transfer from  
SCTDR1 to  
SCTSR1  
TEND  
2
4
FER/ERS  
1
3
Figure 17.12 Retransfer Operation in SCI Transmit Mode  
Rev. 6.0, 07/02, page 727 of 986  
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