14.6
Configuration of the DMAC (SH7750R)
14.6.1
Block Diagram of the DMAC
Figure 14.53 is a block diagram of the DMAC in the SH7750R.
DMAC module
Count control
Registr control
SARn
DARn
DMATCRn
Activation
control
On-chip
peripheral
module
CHCRn
DMAOR
TMU
SCI, SCIF
Request
priority
control
queclr0–7
Bus
interface
DACK0, DACK1
DRAK0, DRAK1
dmaqueclr0-7
8
SAR0, DAR0, DMATCR0,
CHCR0 only
Request
DDT module
,
DTR command buffer
Request controller
32B data
buffer
CH0 CH1 CH2 CH3
DBREQ
/
D[63:0]
ID[1:0]
DDTMODE
BAVL
DDTD
CH4 CH5 CH6 CH7
Bus state
controller
External bus
48 bits
id[2:0]
tdack
DMAORn: DMAC operation register
SARn:
DARn:
DMAC source address register
DMAC destination address register
DMATCRn: DMAC transfer count register
CHCRn:
DMAC channel control register
n = 0 to 7
Figure 14.53 Block Diagram of the DMAC
Rev. 6.0, 07/02, page 574 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
