Address Multiplexing: When area 2 or area 3 is designated as DRAM space, address
multiplexing is always performed in accesses to DRAM. This enables DRAM, which requires row
and column address multiplexing, to be connected to the SH7750 Series without using an external
address multiplexer circuit. Any of the five multiplexing methods shown below can be selected,
by setting bits AMXEXT and AMX2–0 in MCR for area 2 or 3 DRAM. The relationship between
the AMXEXT and AMX2–0 bits and address multiplexing is shown in table 13.15. The address
output pins subject to address multiplexing are A17 to A1. The address signals output by pins A25
to A18 are undefined.
Table 13.15 Relationship between AMXEXT and AMX2–0 Bits and Address Multiplexing
Number
of Column
Address
Setting
External Address Pins
AMXEXT AMX2 AMX1 AMX0 Bits
Output Timing
Column address
Row address
Column address
Row address
Column address
Row address
Column address
Row address
Column address
Row address
—
A1–A13
A1–A13
A9–A21
A1–A13
A14 A15 A16 A17
A14 A15 A16 A17
A22 A23 A24 A25
A14 A15 A16 A17
0
0
0
1
0
0
1
0
1
0
8 bits
9 bits
A10–A22 A23 A24 A25 A17
A1–A13 A14 A15 A16 A17
A11–A23 A24 A25 A16 A17
A1–A13 A14 A15 A16 A17
A12–A24 A25 A15 A16 A17
A1–A13 A14 A15 A16 A17
A13–A25 A14 A15 A16 A17
10 bits
11 bits
12 bits
Reserved
1
Other settings
—
—
—
—
—
Rev. 6.0, 07/02, page 399 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
