INTERRUPTS
6.6 Interrupt priority level detection time
6.6 Interrupt priority level detection time
When the interrupt priority level detection time has passed after sampling starts, an interrupt request is
accepted. The interrupt priority level detection time can be selected by software. (See Figure 6.6.1.) Usually,
select “2 cycles of f
sys
” as the interrupt priority level detection time.
Figure 6.6.2 shows the interrupt priority level detection time.
b7 b6 b5 b4 b3 b2 b1 b0
Processor mode register 0
(Address 5E
16
)
Bit
0
1
2
3
4
5
6
7
Software reset bit
Fix this bit to “0.”
Interrupt priority detection time
select bits
b5 b4
0
Function
X X 0 0
At reset
0
0
0
1
R/W
RW
RW
RW
RW
RW
RW
WO
RW
Bit name
Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1 : Do not select.
1 0 : Do not select.
1 1 : Do not select.
Any of these bits may be either “0” or “1.”
0 0 : 7 cycles of f
sys
0 1 : 4 cycles of f
sys
1 0 : 2 cycles of f
sys
1 1 : Do not select.
The microcomputer is reset by writing “1” to this
bit. The value is “0” at reading.
0
0
0
0
X : It may be either “0” or “1.”
Fig. 6.6.1 Structure of processor mode register 0
f
sys
Op-code fetch cycle
Sampling pulse
(a) 7 cycles of f
sys
Interrupt priority level
detection time
(b) 4 cycles of f
sys
(c) 2 cycles of f
sys
Note:
The pulse resides when “2 cycles of f
sys
” is selected.
(Note)
Fig. 6.6.2 Interrupt priority level detection time
6-12
7906 Group User’s Manual Rev.2.0
RENESAS [ RENESAS TECHNOLOGY CORP ]
