INTERRUPTS
6.3 Interrupt control
Table 6.3.1 Setting of interrupt priority level
Interrupt priority level select bits
Interrupt priority level
Level 0 (Interrupt disabled)
Priority
b1
0
b0
0
b2
0
—
0
1
0
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
Low
1
0
0
1
1
0
0
0
1
0
1
1
1
0
1
1
1
1
High
Table 6.3.2 Enabled interrupt’s levels according to IPL contents
IPL
0
2
IPL
0
1
IPL
0
0
Enabled interrupt’s level
Level 1 and above are enabled.
0
0
1
Level 2 and above are enabled.
Level 3 and above are enabled.
Level 4 and above are enabled.
Level 5 and above are enabled.
Levels 6 and 7 are enabled.
Only level 7 is enabled.
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
All maskable interrupts are disabled.
IPL
IPL
IPL
0
1
2
: Bit 8 in processor status register (PS)
: Bit 9 in processor status register (PS)
: Bit 10 in processor status register (PS)
7906 Group User’s Manual Rev.2.0
6-8
RENESAS [ RENESAS TECHNOLOGY CORP ]
