7906 参数 Datasheet PDF下载

INTERRUPTS

6.5 Interrupt priority level detection circuit

6.5 Interrupt priority level detection circuit

The interrupt priority level detection circuit is used to select the interrupt with the highest priority level from

multiple interrupt requests sampled at the same timing. Figure 6.5.1 shows the interrupt priority level detection

circuit.

Level 0 (Initial value)

Interrupt priority level

Interrupt priority level

Timer A9

UART1 transmit

Timer A8

UART1 receive

Timer A7

UART0 transmit

Timer A6

UART0 receive

Timer A5

Timer B2

INT

7

Timer B1

INT

6

Timer B0

INT

5

Timer A4

INT

4

Timer A3

INT

3

Timer A2

A-D conversion

Timer A1

Timer A0

Interrupt with the highest priority level

IPL

Processor interrupt priority level

Interrupt disable flag (I)

Watchdog timer interrupt

Reset

Acceptance of interrupt request

Fig. 6.5.1 Interrupt priority level detection circuit

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7906 Group User’s Manual Rev.2.0