INTERRUPTS
6.7 Sequence from acceptance of interrupt request until execution of interrupt routine
q
When stack pointer (S)’s contents are even at acceptance of an interrupt request with bus cycle = 2φ
(Note)
f
sys
φ
CPU
AD
23
–AD
16
(Note)
(Note)
Undefined
00
00
00
00
00
00
(Note)
AD
15
–AD
0
(Note)
Undefined
0000
[S]
[S] – 2
[S] – 4
FFXX
16
AD
15
–AD
0
DB
15
–DB
8
(Note)
Undefined
IPL
—
PC
H
PS
H
AD
15
–AD
8
Next instruction
DB
7
–DB
0
(Note)
Undefined
PG
PC
L
PS
L
AD
7
–AD
0
Next instruction
RD
(Note)
Vector address
(low-order)
BLW
BHW
INTACK sequence
[S]: Contents of stack pointer (S)
FFXX
16
: Vector address
f
sys
,
φ
CPU
: Internal clock (See Figure 4.2.1.)
AD
23
–AD
0
: Internal address bus
DB
15
–DB
0
: Internal data bus
Note:
These are internal signals and are not output to the external.
Fig. 6.7.2 INTACK sequence timing (at minimum)
6.7.1 Change in IPL at acceptance of interrupt request
When an interrupt request is accepted, the processor interrupt priority level (IPL) is replaced with the
interrupt priority level of the accepted interrupt. This results in easy control of the processing for multiple
interrupts. (Refer to section
“6.9 Multiple interrupts.”)
At acceptance of a watchdog timer interrupt request, a zero division request, or address matching detection
interrupt request or at reset, a value in Table 6.7.1 is set into the IPL.
Table 6.7.1 Change in IPL at acceptance of interrupt request
Interrupts
Reset
Watchdog timer
Zero division
Address matching detection
Other interrupts
Level 0 (“000
2
”) is set.
Level 7 (“111
2
”) is set.
Not changed.
Not changed.
Accepted interrupt’s priority level is set.
Change in IPL
6-14
7906 Group User’s Manual Rev.2.0
RENESAS [ RENESAS TECHNOLOGY CORP ]
