INTERRUPTS
6.7 Sequence from acceptance of interrupt request until execution of interrupt routine
➀ When stack pointer (S)’s contents are even at acceptance of an interrupt request with bus cycle = 2φ
(Note)
f
sys
(Note)
CPU
φ
(Note)
AD23–AD16
Undefined
Undefined
Undefined
Undefined
00
00
[S]
00
00
00
00
(Note)
AD15–AD
0
0000
[S] – 2
[S] – 4
FFXX16
AD15–AD
0
(Note)
DB15–DB
8
Next instruction
Next instruction
IPL
PCH
PSH
PSL
—
AD15–AD8
(Note)
DB
7
–DB
0
PG
PCL
AD7–AD0
(Note)
RD
Vector address
(low-order)
(Note)
BLW
BHW
INTACK sequence
[S]: Contents of stack pointer (S)
FFXX16: Vector address
sys, φCPU: Internal clock (See Figure 4.2.1.)
f
AD23–AD
DB15–DB
0
: Internal address bus
: Internal data bus
0
Note: These are internal signals and are not output to the external.
Fig. 6.7.2 INTACK sequence timing (at minimum)
6.7.1 Change in IPL at acceptance of interrupt request
When an interrupt request is accepted, the processor interrupt priority level (IPL) is replaced with the
interrupt priority level of the accepted interrupt. This results in easy control of the processing for multiple
interrupts. (Refer to section “6.9 Multiple interrupts.”)
At acceptance of a watchdog timer interrupt request, a zero division request, or address matching detection
interrupt request or at reset, a value in Table 6.7.1 is set into the IPL.
Table 6.7.1 Change in IPL at acceptance of interrupt request
Interrupts
Change in IPL
Reset
Level 0 (“000
Level 7 (“111
Not changed.
Not changed.
2
2
”) is set.
”) is set.
Watchdog timer
Zero division
Address matching detection
Other interrupts
Accepted interrupt’s priority level is set.
7906 Group User’s Manual Rev.2.0
6-14
RENESAS [ RENESAS TECHNOLOGY CORP ]
