7906 参数 Datasheet PDF下载

INTERRUPTS

6.4 Interrupt priority level

6.4 Interrupt priority level

When the interrupt disable flag (I) = “0” (interrupts enabled) and more than one interrupt request is detected

at the same sampling timing, which means a timing to check whether an interrupt request exists or not, they

are accepted in descending sequence from the highest priority level.

A maskable interrupt can be set to the desired priority level by using the interrupt priority level select bits.

The priority levels of reset and a watchdog timer interrupt are set by hardware. Figure 6.4.1 shows the

interrupt priority levels set by hardware.

Note that software interrupts are not affected by the interrupt priority levels. Whenever an instruction is

executed, a branch is certainly made to the interrupt routine.

Reset

Watchdog

timer

••••••••••••••••••

Maskable

interrupts

Priority levels determined by hardware

The user can set the desired priority level to a maskable interrupt.

High

Priority level

Low

Fig. 6.4.1 Interrupt priority levels set by hardware

7906 Group User’s Manual Rev.2.0

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