INTERRUPTS
6.3 Interrupt control
6.3.1 Interrupt disable flag (I)
All maskable interrupts can be disabled by this flag. When this flag is set to “1,” all maskable interrupts
are disabled; when this flag is cleared to “0,” those interrupts are enabled. Because this flag is set to “1”
at reset, clear this flag to “0” when enabling interrupts.
6.3.2 Interrupt request bit
When an interrupt request occurs, this bit is set to “1.” This bit remains set to “1” until the interrupt request
is accepted; it is cleared to “0” when the interrupt request is accepted.
This bit can also be set to “0” or “1” by software.
The INT
i
interrupt request bit (i = 3 to 7) is ignored when the corresponding INT interrupt is used with the
i
level sense.
6.3.3 Interrupt priority level select bits and Processor interrupt priority level (IPL)
The interrupt priority level select bits are used to determine the priority level of each interrupt.
When an interrupt request occurs, its interrupt priority level is compared with the processor interrupt priority
level (IPL). The requested interrupt is enabled only when the comparison result meets the following condition.
Accordingly, any interrupt can be disabled by setting its interrupt priority level to 0.
Each interrupt priority level > Processor interrupt priority level (IPL)
Table 6.3.1 lists the setting of interrupt priority levels, and Table 6.3.2 lists the enabled interrupt’s levels
according to the IPL contents.
The interrupt disable flag (I), interrupt request bit, interrupt priority level select bits, and processor interrupt
priority level (IPL) are independent of one another; they do not affect one another. Interrupt requests are
accepted only when all of the following conditions are satisfied.
•Interrupt disable flag (I) = “0”
•Interrupt request bit = “1”
•Interrupt priority level > Processor interrupt priority level (IPL)
7906 Group User’s Manual Rev.2.0
6-7
RENESAS [ RENESAS TECHNOLOGY CORP ]
