INTERRUPTS
6.3 Interrupt control
6.3 Interrupt control
The maskable interrupts are controlled by the following :
•Interrupt request bit
Assigned to an interrupt control register of each interrupt.
Assigned to the processor status register (PS).
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•Interrupt priority level select bits
•Processor interrupt priority level (IPL)
•Interrupt disable flag (I)
Figure 6.3.1 shows the memory assignment of the interrupt control registers, and Figures 6.3.2 shows their
structures.
Address
6E16
6F16
7016
7116
7216
7316
7416
7516
7616
7716
7816
7916
7A16
7B16
7C16
INT
INT
3
4
interrupt control register
interrupt control register
A-D conversion interrupt control register
UART0 transmit interrupt control register
UART0 receive interrupt control register
UART1 transmit interrupt control register
UART1 receive interrupt control register
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
F516
F616
F716
F816
F916
Timer A5 interrupt control register
Timer A6 interrupt control register
Timer A7 interrupt control register
Timer A8 interrupt control register
Timer A9 interrupt control register
FD16
FE16
FF16
INT
INT
INT
5
6
7
interrupt control register
interrupt control register
interrupt control register
Fig. 6.3.1 Memory assignment of interrupt control registers
7906 Group User’s Manual Rev.2.0
6-5
RENESAS [ RENESAS TECHNOLOGY CORP ]
