INTERRUPTS
6.3 Interrupt control
6.3 Interrupt control
The maskable interrupts are controlled by the following :
•Interrupt request bit
Assigned to an interrupt control register of each interrupt.
•Interrupt priority level select bits
•Processor interrupt priority level (IPL)
Assigned to the processor status register (PS).
•Interrupt disable flag (I)
}
}
Figure 6.3.1 shows the memory assignment of the interrupt control registers, and Figures 6.3.2 shows their
structures.
Address
6E
16
6F
16
70
16
71
16
72
16
73
16
74
16
75
16
76
16
77
16
78
16
79
16
7A
16
7B
16
7C
16
INT
3
interrupt control register
INT
4
interrupt control register
A-D conversion interrupt control register
UART0 transmit interrupt control register
UART0 receive interrupt control register
UART1 transmit interrupt control register
UART1 receive interrupt control register
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
F5
16
F6
16
F7
16
F8
16
F9
16
Timer A5 interrupt control register
Timer A6 interrupt control register
Timer A7 interrupt control register
Timer A8 interrupt control register
Timer A9 interrupt control register
FD
16
FE
16
FF
16
INT
5
interrupt control register
INT
6
interrupt control register
INT
7
interrupt control register
Fig. 6.3.1 Memory assignment of interrupt control registers
7906 Group User’s Manual Rev.2.0
6-5
RENESAS [ RENESAS TECHNOLOGY CORP ]
