INTERRUPTS
6.2 Interrupt sources
6.2 Interrupt sources
Tables 6.2.1 and 6.2.2 list the interrupt sources and the interrupt vector addresses. When programming, set
the start address of each interrupt routine to the vector addresses listed in these tables.
Table 6.2.1 Interrupt sources and interrupt vector addresses (1)
Interrupt vector addresses
Remarks
Low-order
address
FFFE16
FFFC16
FFFA16
FFF816
FFF616
FFF416
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
FFE416
FFE216
FFE016
FFDE16
FFDC16
FFDA16
FFD816
FFD616
FFD416
FFD216
FFD016
FFCE16
FFCC16
FFCA16
FFC816
FFC616
FFC416
FFC216
Interrupt source
Reset
High-order
address
FFFF16
FFFD16
FFFB16
FFF916
FFF716
FFF516
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFE516
FFE316
FFE116
FFDF16
FFDD16
FFDB16
FFD916
FFD716
FFD516
FFD316
FFD116
FFCF16
FFCD16
FFCB16
FFC916
FFC716
FFC516
FFC316
Reference
3. RESET
Non-maskable
Non-maskable software interrupt
Do not use.
Zero division
BRK instruction (Note)
DBC (Note)
Watchdog timer
Reserved area
Reserved area
Reserved area
Reserved area
Timer A0
7900 Series Software Manual
Non-maskable internal interrupt
Do not use.
14. WATCHDOG TIMER
Maskable internal interrupts
7. TIMER A
Timer A1
Timer A2
Timer A3
Timer A4
Maskable internal interrupts
Maskable internal interrupts
Timer B0
8. TIMER B
Timer B1
Timer B2
11. SERIAL I/O
UART0 receive
UART0 transmit
UART1 receive
UART1 transmit
A-D conversion
Maskable internal interrupt
Maskable external interrupts
12. A-D CONVERTER
6.10 External interrupts
INT
INT
3
4
Reserved area
Do not use.
Reserved area
Address matching detection
Reserved area
17. DEBUG FUNCTION
6.10 External interrupts
Non-maskable software interrupt
Do not use.
INT
INT
INT
5
6
7
Maskable external interrupts
Note: The BRK instruction and the DBC interrupt are used exclusively for a debugger.
➀➀Maskable interrupt: An interrupt of which request’s acceptance can be disabled by software.
➀➀Non-maskable interrupt (including zero division, watchdog timer, and address matching detection interrupts):
An interrupt which is certain to be accepted when its request occurs. These interrupts do not have their
interrupt control registers and are not affected by the interrupt disable flag (I).
7906 Group User’s Manual Rev.2.0
6-3
RENESAS [ RENESAS TECHNOLOGY CORP ]
