INTERRUPTS
6.2 Interrupt sources
6.2 Interrupt sources
Tables 6.2.1 and 6.2.2 list the interrupt sources and the interrupt vector addresses. When programming, set
the start address of each interrupt routine to the vector addresses listed in these tables.
Table 6.2.1 Interrupt sources and interrupt vector addresses (1)
Interrupt vector addresses
Interrupt source
Reset
Zero division
BRK
instruction
(Note)
High-order Low-order
address
address
FFFF
16
FFFD
16
FFFB
16
FFF9
16
FFF7
16
FFF5
16
FFF3
16
FFF1
16
FFEF
16
FFED
16
FFEB
16
FFE9
16
FFE7
16
FFE5
16
FFE3
16
FFE1
16
FFDF
16
FFDD
16
FFDB
16
FFD9
16
FFD7
16
FFD5
16
FFD3
16
FFD1
16
FFCF
16
FFCD
16
FFCB
16
FFC9
16
FFC7
16
FFC5
16
FFC3
16
FFFE
16
FFFC
16
FFFA
16
FFF8
16
FFF6
16
FFF4
16
FFF2
16
FFF0
16
FFEE
16
FFEC
16
FFEA
16
FFE8
16
FFE6
16
FFE4
16
FFE2
16
FFE0
16
FFDE
16
FFDC
16
FFDA
16
FFD8
16
FFD6
16
FFD4
16
FFD2
16
FFD0
16
FFCE
16
FFCC
16
FFCA
16
FFC8
16
FFC6
16
FFC4
16
FFC2
16
Do not use.
Remarks
Non-maskable
Non-maskable software interrupt
Do not use.
Non-maskable internal interrupt
Do not use.
Reference
3. RESET
7900 Series Software Manual
DBC
(Note)
Watchdog timer
Reserved area
Reserved area
Reserved area
Reserved area
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Timer B0
Timer B1
Timer B2
UART0 receive
UART0 transmit
UART1 receive
UART1 transmit
A-D conversion
INT
3
INT
4
Reserved area
Reserved area
Address matching detection
14. WATCHDOG TIMER
Maskable internal interrupts
7. TIMER A
Maskable internal interrupts
8. TIMER B
Maskable internal interrupts
11. SERIAL I/O
Maskable internal interrupt
Maskable external interrupts
12. A-D CONVERTER
6.10 External interrupts
Non-maskable software interrupt 17. DEBUG FUNCTION
Do not use.
Maskable external interrupts
6.10 External interrupts
Reserved area
INT
5
INT
6
INT
7
Note:
The
BRK
instruction and the DBC interrupt are used exclusively for a debugger.
q
Maskable interrupt:
An interrupt of which request’s acceptance can be disabled by software.
q
Non-maskable interrupt
(including zero division, watchdog timer, and address matching detection interrupts):
An interrupt which is certain to be accepted when its request occurs. These interrupts do not have their
interrupt control registers and are not affected by the interrupt disable flag (I).
7906 Group User’s Manual Rev.2.0
6-3
RENESAS [ RENESAS TECHNOLOGY CORP ]
