CENTRAL PROCESSING UNIT (CPU)
2.2 Bus interface unit (BIU)
2.2 Bus interface unit (BIU)
The bus interface unit (hereafter called “BIU”) performs the following two operations:
ꢀ Instruction prefetch
ꢀꢀData transfer (read and write)
Figure 2.2.1 shows the bus and BIU.
BIU is structured with four kinds of registers shown in Figure 2.2.2. Table 2.2.1 lists the function of the BIU
registers.
M37906
Internal buses
CPU bus
Internal code bus (CB
0
to CB31
to DB15
to AD23
)
Bus
interface
unit
Central
processing
unit
Internal data bus (DB
0
)
Internal
memory
Internal address bus (AD
Internal control signal
0
)
(BIU)
(CPU)
Internal
peripheral
devices
(SFR)
SFR : Special Function Register
ꢀ The CPU bus and internal bus are independent of one another.
Fig. 2.2.1 Bus and BIU
Table 2.2.1 Functions of BIU registers
b0
b0
b23
Name
Program
address
register
Instruction
queue buffer
Functions
PA
Program address register
Instruction queue buffer
Indicates a storage address of the
instruction to be fetched into an
instruction queue buffer, next.
Temporarily stores an instruction
which has been fetched.
b7
Q
Q
0
9
Data address Indicates an address from which data
register
will be read or to which data will be
written, next.
Temporarily stores data which has
been read from memory•I/O device
by BIU or which will be written to
memory•I/O device by the CPU.
b23
b0
b0
DA
Data address register
Data buffer
Data buffer
b31
DQ
Fig. 2.2.2 BIU registers’ structure
In the M37906, the internal buses are used when the CPU accesses the internal area (the internal memory
and SFR).
7906 Group User’s Manual Rev.2.0
2-10
RENESAS [ RENESAS TECHNOLOGY CORP ]
