SERIAL I/O
11.4 Clock asynchronous serial I/O (UART) mode
UART0 transmit/receive mode register (Address 3016
UART1 transmit/receive mode register (Address 3816
)
)
b7
b0
1
UART0 baud rate register (BRG0) (Address 3116
UART1 baud rate register (BRG1) (Address 3916
)
)
Serial I/O mode select bit
b2 b1 b0
1
1
1
0
0
1
0: UART mode (7 bits)
1: UART mode (8 bits)
0: UART mode (9 bits)
b7
b0
Internal/External clock select bit
0: Internal clock
1: External clock
Can be set to “0016” to “FF16.”
Stop bit length select bit
0: 1 stop bit
1: 2 stop bits
Port P1 direction register (Address 516
b7 b0
)
Odd/Even parity select bit
0: Odd parity
1: Even parity
0
0
Pin RxD
Pin RxD
0
1
Parity enable bit
0: Parity is disabled.
1: Parity is enabled.
Sleep select bit
0: Sleep mode cleared (invalid)
1: Sleep mode selected
UART0 receive interrupt control register (Address 7216
UART1 receive interrupt control register (Address 7416
)
)
✕✕Set the same transfer data format
as that of the transmitter side.
b7
b0
UART0 transmit/receive control register 0 (Address 3416
UART1 transmit/receive control register 0 (Address 3C16
)
)
Interrupt priority level select bits
When using interrupts, set these bits to
one of levels 1 to 7.
When disabling interrupts, set these bits
to level 0.
b7
b0
0
0
BRG count source select bits
b1 b0
0 0 : f
2
0 1 : f16
1 0 : f64
1 1 : f512
UART0 transmit/receive control register 1 (Address 3516
UART1 transmit/receive control register 1 (Address 3D16
b7 b0
)
)
1
CTS/RTS function select bit
0: CTS function selected
1: RTS function selected
Receive enable bit
1: Reception enabled
CTS/RTS enable bit
0: CTS/RTS function is enabled.
1: CTS/RTS function is disabled.
UARTi receive interrupt mode select bit
0: Reception interrupt
1: Reception error interrupt
Reception will start when the start bit (’s
Serial I/O pin control register (Address AC16
b7 b0
)
falling edge) is detected.
CTS
0
/RTS
0
separate select bit
0: CTS
1: CTS
0
/RTS
/RTS
0
are used together.
are separated (Note 1).
0
0
CTS1/RTS1 separate select bit
0: CTS
1: CTS
1
/RTS
/RTS
1
are used together.
are separated (Note 1).
1
1
TxD
0: Functions as TxD
1: Functions as P1
0/P13 switch bit (Note 2)
0.
3.
TxD /P1 switch bit (Note 2)
0: Functions as TxD
1: Functions as P1
1
7
1.
7.
Notes 1: The CLK
i
pin cannot be used
/RTS separation
when the CTS
i
i
is selected. (Refer to “[Precau-
tion for clock asynchronous
serial I/O (UART) mode].”)
2: When performing reception only,
if these bits are set to “1,” the
TxDi pin can be used as a
programmable I/O port pin.
Fig. 11.4.10 Initial setting example for relevant registers when receiving
7906 Group User’s Manual Rev.2.0
11-48
RENESAS [ RENESAS TECHNOLOGY CORP ]
