SERIAL I/O
11.4 Clock asynchronous serial I/O (UART) mode
Tc
Transfer clock
Transmit enable bit
Data is set in UARTi transmit buffer register.
Transmit buffer
empty flag
UARTi transmit register
← UARTi transmit buffer register
T
ENDi
Stopped because transmit enable bit = “0”
ST
ST
D0
D1
D2
D3
D4
D5
D7
D
8
ST
D0
D1
D2
D3
D4
D5
D7
D8
D0
D1
D6
SP SP
D6
SP SP
TxDi
Transmit register
empty flag
UARTi transmit
interrupt request bit
Cleared to “0” when interrupt request is accepted or cleared to “0” by software.
The above timing diagram applies when
the following conditions are satisfied:
✕ Parity disabled
✕ 2 stop bits
✕ CTS function not selected
T
ENDi: Next transmit conditions are examined when this signal level
ST: Start bit
to D : Transfer data
P: Parity bit
ST: Stop bit
becomes “H.”
D
0
7
(TENDi is an internal signal. Accordingly, it cannot be read from
the external.)
Tc = 16 (n + 1)/fi or 16 (n + 1)/fEXT
fi
: BRGi count source frequency (internal clock)
fEXT: BRGi count source frequency (external clock)
n: Value set in BRGi
Fig. 11.4.9 Example of transmit timing when transfer data length = 9 bits (when parity disabled,
2 stop bits selected, CTS function not selected)
7906 Group User’s Manual Rev.2.0
11-46
RENESAS [ RENESAS TECHNOLOGY CORP ]
