SERIAL I/O
11.4 Clock asynchronous serial I/O (UART) mode
11.4.6 Receive operation
When the receive enable bit is set to “1,” the UARTi enters the receive-enabled state. Then, reception will
start when ST (’s falling edge) is detected and a transfer clock is generated.
If the RTS function selected, when connecting the RTS
i
pin to the CTS pin of the transmitter side, the
i
timing of transmission and that of reception can be matched. If the RTS function selected, the RTS
output level becomes as described below.
i
pin’s
When the receive enable bit = “0,” if one of the following is performed, the RTS
“L” and informs of the transmitter side that reception has become enabled:
• The receive enable bit is set to “1.”
i
pin’s output level becomes
• The low-order byte of the UARTi receive buffer register is read out.
When the receive enable bit = “1,” if the low-order byte of the UARTi receive buffer register is read out,
the RTS pin’s output level becomes “L.”
i
Accordingly, when performing reception continuously, an overrun occurrence can be avoided because the
RTS output level does not become “L” until the receive data is read out.
When reception has started, the RTS pin’s output level becomes “H.”
i
Figure 11.4.12 shows a connection example.
Transmitter side
Receiver side
TxD
i
TxD
i
RxD
i
RxDi
CTS
i
RTSi
Fig. 11.4.12 Connection example
The receive operation is described below.
✕ The signal input to the RxD pin is taken into the most significant bit of the UARTi receive register,
i
synchronously with the transfer clock’s rising edge.
✕ The contents of the UARTi receive register are shifted, bit by bit, to the right.
✕ Steps ✕ and ✕ are repeated at each rising edge of the transfer clock.
✕✕When one set of data has been prepared, in other words, when the shift operation has been performed
several times according to the selected data format, the UARTi receive register’s contents are transferred
to the UARTi receive buffer register.
✕ Simultaneously with step ✕, the receive complete flag is set to “1.” Additionally, when the receive
interrupt is selected (UARTi receive interrupt mode select bit = “0”), a UARTi receive interrupt request
occurs and its interrupt request bit is set to “1.”
The receive complete flag is cleared to “0” when the low-order byte of the UARTi receive buffer register
has been read out. Figure 11.4.13 shows an example of receive timing when the transfer data length = 8
bits.
7906 Group User’s Manual Rev.2.0
11-50
RENESAS [ RENESAS TECHNOLOGY CORP ]
