SERIAL I/O
11.4 Clock asynchronous serial I/O (UART) mode
Tc
Transfer clock
Transmit enable bit
Data is set in UARTi transmit buffer register.
Transmit buffer
empty flag
UARTi transmit register
← UARTi transmit buffer register
T
ENDi
Stopped because transmit enable bit = “0”
TxD
i
ST
D
0
D1
ST
D0
D1
D2
D3
D4
D5
D7
P
SP ST
D0
D1
D2
D3
D4
D5
D7
P
SP
D6
D6
Transmit register
empty flag
UARTi transmit
interrupt request bit
Cleared to “0” when interrupt request is accepted or cleared to “0” by software.
The above timing diagram applies when
the following conditions are satisfied:
✕ Parity enabled
✕ 1 stop bit
✕ CTS function not selected
ST: Start bit
to D : Transfer data
P: Parity bit
ST: Stop bit
T
ENDi: Next transmit conditions are examined when this signal level
D
0
7
becomes “H.”
(TENDi is an internal signal. Accordingly, it cannot be read from
the external.)
Tc: 16 (n + 1)/fi or 16 (n + 1)/fEXT
f
i: BRGi’s count source frequency (internal clock)
fEXT: BRGi’s count source frequency (external clock)
n: Value set in BRGi
Fig. 11.4.7 Example of transmit timing when transfer data length = 8 bits (when parity enabled,
1 stop bit selected, CTS function not selected)
Tc
Transfer clock
Transmit enable bit
Data is set in UARTi transmit buffer register.
Transmit buffer
empty flag
UARTi transmit register
← UARTi transmit buffer register
CTS
i
TENDi
Stopped because transmit
enable bit = “0”
Stopped because CTSi = “H”
ST
ST
TxDi
D0
D1
ST
D0
D1
D2
D3
D4
D5
D7
P
D0
D1
D2
D3
D4
D5
D7
P
D6
SP
D6
SP
Transmit register
empty flag
UARTi transmit
interrupt request bit
Cleared to “0” when interrupt request is accepted or cleared to “0” by software.
The above timing diagram applies
when the following conditions are
satisfied:
✕ Parity enabled
✕ 1 stop bit
T
ENDi: Next transmit conditions are examined when this signal level
ST: Start bit
to D : Transfer data
P: Parity bit
ST: Stop bit
becomes “H.”
D
0
7
(TENDi is an internal signal. Accordingly, it cannot be read from
the external.)
✕ CTS function selected
Tc = 16 (n + 1)/fi or 16 (n + 1)/fEXT
f
i
: BRGi’s count source frequency (internal clock)
f
EXT: BRGi’s count source frequency (external clock)
n: Value set in BRGi
Fig. 11.4.8 Example of transmit timing when transfer data length = 8 bits (when parity enabled,
1 stop bit and selecting CTS function selected)
7906 Group User’s Manual Rev.2.0
11-45
RENESAS [ RENESAS TECHNOLOGY CORP ]
