SERIAL I/O
11.4 Clock asynchronous serial I/O (UART) mode
BRGi’s count
source
Receive enable
bit
Stop bit
Start bit
D0
D1
D7
RxDi
Received data taken in
Sampled “L”
Transfer clock
At falling edge of start bit, the transfer
clock is generated and reception started.
UARTi receive register → UARTi receive buffer register
Receive
complete flag
RTS
i
UARTi receive buffer register’s reading out
UARTi receive
interrupt
request bit
Cleared to “0” when interrupt request
is accepted or cleared to “0” by
software.
The above timing diagram applies when the following
conditions are satisfied:
✕ Parity disabled
✕ 1 stop bit
✕ RTS function selected
Fig. 11.4.13 Example of receive timing when transfer data length = 8 bits (when parity disabled, 1
stop bit and RTS function selected)
7906 Group User’s Manual Rev.2.0
11-51
RENESAS [ RENESAS TECHNOLOGY CORP ]
