A-D CONVERTER
12.2 Block description
12.2.2 A-D register i (i = 0 to 11)
Figures 12.2.5 and 12.2.6 show the structures of the A-D register i. When the A-D conversion is completed,
the conversion result (contents of the successive approximation register) is stored into this register. When
the comparator function is selected, the value to be compared is stored in this register.
Each A-D register i corresponds to an analog input pin (AN ).
i
❈❈When 8-bit resolution mode is selected
A-D register 0 (Addresses 2116, 2016)
A-D register 1 (Addresses 2316, 2216)
A-D register 2 (Addresses 2516, 2416)
A-D register 3 (Addresses 2716, 2616)
A-D register 4 (Addresses 2916, 2816)
A-D register 5 (Addresses 2B16, 2A16)
A-D register 6 (Addresses 2D16, 2C16)
A-D register 7 (Addresses 2F16, 2E16)
A-D register 8 (Addresses E116, E016)
A-D register 9 (Addresses E316, E216)
A-D register 10 (Addresses E516, E416)
A-D register 11 (Addresses E716, E616)
(b15)
b7
(b8)
b0 b7
b0
Bit
Function
At reset R/W
7 to 0 Reads an A-D conversion result.
15 to 8 The value is “0” at reading.
Undefined RO
0
–
❈❈When 10-bit resolution mode is selected
A-D register 0 (Addresses 2116, 2016)
A-D register 1 (Addresses 2316, 2216)
A-D register 2 (Addresses 2516, 2416)
A-D register 3 (Addresses 2716, 2616)
A-D register 4 (Addresses 2916, 2816)
A-D register 5 (Addresses 2B16, 2A16)
A-D register 6 (Addresses 2D16, 2C16)
A-D register 7 (Addresses 2F16, 2E16)
A-D register 8 (Addresses E116, E016)
A-D register 9 (Addresses E316, E216)
A-D register 10 (Addresses E516, E416)
A-D register 11 (Addresses E716, E616)
(b8)
b0
(b15)
b7
b7
b0
Bit
Function
At reset R/W
Undefined RO
9 to 0 Reads an A-D conversion result.
15 to 10 The value is “0” at reading.
0
–
Fig. 12.2.5 Structure of A-D register i (1)
7905 Group User’s Manual Rev.1.0
12-10
RENESAS [ RENESAS TECHNOLOGY CORP ]
