RTL8208B-LF/RTL8208BF-LF
Datasheet
Since this configuration is a loopback connection, it uses full duplex only. Half duplex is not supported.
The loopback-pair ports should be configured to the same speed. Although this mode does not effect
normal NWay mode, in order to keep each pair’s two ports at the same speed, there is an auto-detection
scheme. This scheme specifies that if one port of the pair is already linked, when the other port is linked
later, the earlier link-on port will re-start auto negotiation. When PP-LPBK mode is set, there are three
requirements: it must be based upon RMII mode; no switch controller can be connected; and TX_EN[7:0]
must be pulled down.
7.1.3. PHY Address
Each transceiver in the RTL8208B(F)-LF has a unique PHY address for MII management. The address is
set through the PHY address pins. The pins are latched at the trailing end of a reset. Transceiver 1 will
have the address AA000, where AA=PHYAD [4:3]. Each internal PHY address is AA000, AA001,
AA010, AA011, AA100, AA101, AA110, AA111. Every time an SMI write or read operation is executed,
the transceiver compares the PHY address with its own PHY address definition, and the operation is
executed only when the addresses match.
7.1.4. Auto-Negotiation
For 10/100Mbps TP ports, the RTL8208B(F)-LF default setup is Auto-Negotiation enabled. Setting
Register 0.12=0 via an SMI write will disable Auto-Negotiation. For a 100FX port, Auto-Negotiation is
always disabled.
For an Auto-Negotiation enabled port, the RTL8208B(F)-LF will negotiate with its link partner to
determine the speed and duplex status. The RTL8208B(F)-LF’s ability is advertised in Register 4. After
Auto-Negotiation is finished, the link partner’s ability is stored in Register 5.
If the link partner is Auto-Negotiation disabled, the RTL8208B(F)-LF enters a parallel-detection state to
identify the speed of the link partner. The RTL8208B(F)-LF will link at the same speed as the link partner,
in half duplex mode if FRC_PARA_FULL=0 upon reset, or in full duplex mode if FRC_PARA_FULL=1
upon reset.
Auto-Negotiation is also used to determine full-duplex flow control. Flow control ability is advertised in
Register 4.10. The link partner’s flow control ability is stored in Register 5.10. See the following section
for more information.
7.1.5. Full-Duplex Flow Control
If hardware pins TP_PAUSE or FX_PAUSE are enabled at power-on reset, Register 5.10=1 and Register
4.10=1. Therefore, after reset is completed:
When Auto-Negotiation is enabled -- Register 4.10 may be overwritten by the MAC, and Register 5.10
may be updated after NWay has completed. Register 5.10 is set as read-only for the MAC.
When Auto-Negotiation is disabled -- Register 5.10 is set to R/W for the MAC through the SMI
interface. If the SMI does not write to Register 5.10, the Register remains 5.10=1, which means hardware
forced flow control is enabled.
Single-Chip Octal 10/100-TX/FX PHY Transceiver
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Track ID: JATR-1076-21 Rev. 1.3
REALTEK [ Realtek Semiconductor Corp. ]
